PHASE LOCKED LOOP CIRCUIT
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United States of America Patent
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Issued Date -
Mar 26, 2015
app pub date -
Aug 27, 2014
filing date -
Sep 26, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A Phase Locked Loop (PLL) circuit is provided. The PLL includes a voltage controlled oscillator (VCO) for outputting an oscillation signal of a frequency corresponding to an inputted voltage, a frequency divider for dividing the oscillation signal and output a frequency-divided signal, a phase comparator for comparing a phase of the frequency-divided signal and the phase of an input signal from the outside and output a first phase comparison signal and a second phase comparison signal which have different polarities, a differential amplifier circuit for outputting a control voltage based on a voltage difference between the first phase comparison signal and the second phase comparison signal to the VCO, a level shift circuit for outputting a level-shifted signal which is made by shifting a direct current level of the second phase comparison signal, and an amplifier circuit for outputting an amplified signal which is an amplified level-shifted signal.
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