INTEGRATED CIRCUIT VIA STRUCTURE AND METHOD OF FABRICATION
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United States of America Patent
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Issued Date -
Mar 19, 2015
app pub date -
Sep 18, 2013
filing date -
Sep 18, 2013
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Abandoned
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Abstract
A method for creating one or more vias in an integrated circuit structure and the integrated circuit structure. The method includes depositing a coating layer over a hard mask layer on the integrated circuit structure; locating an initial via pattern layer over the coating layer; and etching the pattern of the one or more initial openings in the coating layer and through openings in the hard mask layer. The coating layer is a conformal deposition of an oxide, a boron nitride, or other nitride. The initial via pattern layer has one or more initial openings located therein.
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