Method for forming through wafer vias
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United States of America Patent
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Issued Date -
Mar 12, 2015
app pub date -
Sep 11, 2013
filing date -
Sep 11, 2013
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Abandoned
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Abstract
A method for forming through substrate vias (TSVs) in a non-conducting, glass substrate is disclosed. The method involves patterning a silicon template substrate with a plurality of lands and spaces, bonding a slab or wafer of glass to the template substrate, and melting the glass so that it flows into the spaces formed in the template substrate. The template substrate may then be removed to leave a plurality of TSVs in the glass slab or wafer.
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