POWER SEMICONDUCTOR DEVICE WITH SUPER JUNCTION STRUCTURE AND INTERLACED, GRID-TYPE TRENCH NETWORK
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
N/A
app pub date -
Oct 26, 2014
filing date -
Jan 25, 2013
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A power semiconductor device includes a semiconductor wafer having thereon a plurality of die regions and scribe lanes between the die regions. A first epitaxial layer is disposed on the semiconductor wafer. First trenches extend along a first direction and traverse the plurality of die regions and the scribe lanes. Second trenches extend along a second direction and traverse the plurality of die regions and the scribe lanes. The first direction is perpendicular to the second direction. The first trenches intersect the second trenches to thereby form an interlaced, grid-type trench network.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully