FINE-PITCH PILLAR BUMP LAYOUT STRUCTURE ON CHIP
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United States of America Patent
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Issued Date -
Feb 19, 2015
app pub date -
Aug 16, 2013
filing date -
Aug 16, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Disclosed is a fine-pitch pillar bump layout structure on chip, comprising a chip, a passivation layer and at least two pillar bumps. Bonding pads of the chip are disposed along an X-axis. Openings of the passivation layer have a first aspect ratio. Pillar bumps are disposed on the bonding pads and each has a pillar body and a solder cap. Each pillar body has a plurality of symmetrical raised blocks disposed on the passivation layer and extended in both directions of Y-axis. The pillar bodies have shrunk bump widths along the X-axis so that a second aspect ratio is at least 1.5 times greater than the first aspect ratio and to partially expose the bonding pads and to make the central points of the pillar bodies be vertically aligned with the central points of the openings of the passivation layer.
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