MEMORY CELL HAVING BUILT-IN WRITE ASSIST
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United States of America Patent
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Issued Date -
Feb 12, 2015
app pub date -
Mar 27, 2014
filing date -
Aug 8, 2013
priority date (Note) -
Abandoned
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Abstract
A memory cell includes a storage element including a pair of cross-coupled inverters, and first switching circuitry for selectively connecting at least one internal storage node of the storage element with a corresponding bit line as a function of a first control signal. Write assist circuitry is connected between a supply node of a device of at least one of the cross-coupled inverters and a voltage supply of the memory cell, and second switching circuitry selectively couples the supply node of the device of at least one of the cross-coupled inverters with the corresponding bit line as a function of a second control signal. During a write operation, the write assist circuitry disconnects the storage element from the voltage supply, and the second circuitry connects the supply node of the device of at least one of the cross-coupled inverters with the corresponding bit line.
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