ESD CLAMP CIRCUIT
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United States of America Patent
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Issued Date -
Feb 12, 2015
app pub date -
Aug 6, 2013
filing date -
Aug 6, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
ESD clamp circuit is provided, including an RC circuit, a first transistor, a second transistor, an ESD conduction unit and an inverter. The first transistor has a gate and a drain respectively coupled to the RC circuit and a control terminal of the ESD conduction unit. The inverter has an input terminal coupled to the control terminal. The second transistor has a drain and a gate respectively coupled to the control terminal and an output terminal of the inverter. The gates of the first and second transistors are isolated; also the output terminal and the gate of the first transistor are isolated.
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