TEST MUX FLIP-FLOP CELL FOR REDUCED SCAN SHIFT AND FUNCTIONAL SWITCHING POWER CONSUMPTION
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United States of America Patent
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Issued Date -
Feb 5, 2015
app pub date -
Jul 30, 2013
filing date -
Jul 30, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A new flip-flop cell that is more efficient in scan chain configuration includes a multiplexer, storage element (e.g., a flip-flop), an inverter, and multiple logic gates. The flip-flop cell is configured to receive both a test signal and a data input signal and select one of the two to pass to the storage element based on a scan enable signal that indicates either a capture mode or a scan shift mode. In capture mode, the data input signal is passed to the storage element, and the internal outputs of the flip-flop are supplied to the logic gates. Based on the internal outputs and scan enable signal, the logic gates disable either one of two outputs of the flip-flop cell. In capture mode, a test flip-flop cell output is disabled. In scan shift mode, a standard function flip-flop cell output is disabled.
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