Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability

Number of patents in Portfolio can not be more than 2000

United States of America Patent

SERIAL NO

14486421

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

First Claim

See full text

Other Claims data not available

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
MONTEREY RESEARCH LLC3945 FREEDOM CIRCLE SUITE 900 SANTA CLARA CA 95054

International Classification(s)

loading....
  • 2014 Application Filing Year
  • H01L Class
  • 23828 Applications Filed
  • 21803 Patents Issued To-Date
  • 91.51 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2014201520162017201820192020202120222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Tung-Sheng Cupertino, US 17 67
Fang, Shenqing Fremont, US 127 970

Cited Art Landscape

Load Citation

Patent Citation Ranking

  • 0 Citation Count
  • H01L Class
  • 0 % this patent is cited more than
  • 10 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges1377800619237183722181459473474314501 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05001000150020002500300035004000450050005500600065007000750080008500

Forward Cite Landscape

Load Citation