VERTICAL TRANSISTORS HAVING P-TYPE GALLIUM NITRIDE CURRENT BARRIER LAYERS AND METHODS OF FABRICATING THE SAME
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United States of America Patent
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Issued Date -
Jan 15, 2015
app pub date -
Jul 9, 2014
filing date -
Jul 11, 2013
priority date (Note) -
Abandoned
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Abstract
A vertical transistor includes a drain electrode disposed on a first region of a substrate, a drift layer disposed on a second region of the substrate spaced apart from the first region, and P-type gallium nitride current barrier layers disposed on the drift layer and comprising a current aperture disposed between current barrier layers. A channel layer is disposed on the drift layer and the current barrier layers. A semiconductor layer is disposed on the channel layer and configured to induce formation of a two-dimension electron gas layer adjacent to a top surface thereof. Metal contact plugs are disposed in the channel layer and contact the current barrier layers. A source electrode is disposed on the contact plugs and the channel layer. A gate insulation layer and a gate electrode are sequentially disposed on a top surface of the semiconductor layer opposite to the channel layer.
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