AGILE DECODER
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United States of America Patent
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Issued Date -
Nov 20, 2014
app pub date -
Aug 1, 2014
filing date -
Feb 16, 2005
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Abstract
A decoder arrangement (10) includes a processor (12) programmed to decode multiple streams (111-11n), including multiple streams of different formats. In terms of functionality, the decoder arrangement includes a routing stage (13) routes each streams to different decoder stages (141-14n), each capable of decoding a stream of a particular format to yield an uncompressed stream at its output. Each of plurality of buffer stages (161-16n) stores a successive frame of an uncompressed stream output by an associated decoder stage. An output stage scales and the frames stored by the buffer stages to a common size for input to a display device (22).
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