TECHNIQUES FOR THE CANCELLATION OF CHIP SCALE PACKAGING PARASITIC LOSSES

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United States of America Patent

APP PUB NO 20140339688A1
SERIAL NO

14278901

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention generally relates to techniques and structures that cancel or mitigate RF coupling from the RF circuit to the silicon die. To cancel or mitigate the RF coupling, a conductive coating may be formed over the RF-MEMS device. The conductive coating may be coupled to the die. Alternatively, the conductive coating may be coupled to the die through the RF-MEMS by having a through silicon via. Another manner for cancelling or mitigating RF coupling is to have no conductive traces located on the front side of the PCB.

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Patent Owner(s)

Patent OwnerAddress
CAVENDISH KINETICS INC2960 NORTH 1ST STREET SAN JOSE CA 95134

International Classification(s)

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  • 2014 Application Filing Year
  • B81B Class
  • 486 Applications Filed
  • 362 Patents Issued To-Date
  • 74.49 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances201420152016201720182019202020210255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CASTILLOU, Paul Albert San Jose, US 1 4
GADDI, Roberto 's-Hertogenbosch, NL 26 176
SHINGAL, Atul Prakash Fremont, US 1 4
VAN, KAMPEN Robertus Petrus S-Hertogenbosch, NL 43 282
YOST, Dennis J Los Gatos, US 10 98

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Patent Citation Ranking

  • 4 Citation Count
  • B81B Class
  • 0 % this patent is cited more than
  • 11 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges21211 - 1011 - 2031 - 4071 - 8000.10.20.30.40.50.60.70.80.911.11.21.31.41.51.61.71.81.922.1

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