PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE
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United States of America Patent
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app pub date -
Jul 22, 2014
filing date -
Jan 16, 2012
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Abstract
A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are “self aligned” to a “Sacrificial Poly” layer, which later on is removed, preparing the wafers for a “late gate” oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET.
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