LAMINATED STRUCTURE, FERROELECTRIC GATE THIN FILM TRANSISTOR, AND FERROELECTRIC THIN FILM CAPACITOR

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United States of America Patent

APP PUB NO 20140339550A1
SERIAL NO

14359262

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Abstract

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Provided is a ferroelectric gate thin film transistor which includes: a channel layer; a gate electrode layer which controls a conductive state of the channel layer; and a gate insulation layer which is arranged between the channel layer and the gate electrode layer and is formed of a ferroelectric layer. The gate insulation layer (ferroelectric layer) has the structure where a PZT layer and a BLT layer (Pb diffusion preventing layer) are laminated to each other. The channel layer (oxide conductor layer) is arranged on a surface of the gate insulation layer (ferroelectric layer) on a BLT layer (Pb diffusion preventing layer) side. The ferroelectric gate thin film transistor can overcome various drawbacks which may be caused due to the diffusion of Pb atoms into an oxide conductor layer from a PZT layer including a drawback that a transmission characteristic of a ferroelectric gate thin film transistor is liable to be deteriorated (for example, a width of a memory window is liable to become narrow).

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Patent OwnerAddress
JAPAN SCIENCE AND TECHNOLOGY AGENCY4-1-8 HON-CHO KAWAGUCHI-SHI SAITAMA 332-0012

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Miyasako, Takaaki Yokkaichi-shi, JP 17 59
Shimoda, Tatsuya Nomi-shi, JP 214 10119
Tokumitsu, Eisuke Minato-ku, JP 9 56
Trinh, Bui Nguyen Quoc Thanh Xuan, VN 1 3

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