General structure for computational random access memory (CRAM)
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United States of America Patent
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Dec 29, 2015
Grant Date -
Nov 13, 2014
app pub date -
Apr 23, 2014
filing date -
Apr 24, 2013
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Abstract
A cell array includes a logic connection line, a plurality of bit selection lines, and a plurality of cells. Each cell includes a memory element connected to a respective bit selection line and a logic switching element that selectively connects the memory element to the logic connection line. When logic switching elements of multiple separate cells connect their respective memory elements to the logic connection line, the memory elements connected to the logic connection line operate as a logic device with an output of the logic device stored in one of the memory elements.
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