SYSTEMS AND METHODS FOR VOID REDUCTION IN A SOLDER JOINT
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United States of America Patent
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Nov 6, 2014
app pub date -
Sep 25, 2012
filing date -
Sep 26, 2011
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Abstract
In accordance with one or more aspects, a method of reducing void formation in a solder joint may comprise applying a solder paste deposit to a substrate, placing a solder preform in the solder paste deposit, disposing a device on the solder preform and the solder paste deposit, and processing the solder paste deposit and the solder preform to form the solder joint between the device and the substrate. In some aspects, the substrate is a printed circuit board and the device is an integrated circuit package.
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