METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY

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United States of America Patent

APP PUB NO 20140308807A1
SERIAL NO

14249357

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Abstract

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A method for fabricating a semiconductor memory includes the following steps. Active areas are defined in a substrate. An oxide layer is then formed on the active areas. The oxide layer is subjected to a surface treatment. A first polysilicon layer, a buffer layer and a hard mask are deposited. Recessed access devices are formed in an array region of the substrate. After the recessed access devices are formed, the hard mask and the buffer layer are removed to thereby form transistors in a peripheral region. A second polysilicon layer is deposited on the first polysilicon layer. The first and second polysilicon layers are then etched into a gate structure.

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Patent Owner(s)

Patent OwnerAddress
INOTERA MEMORIES INCNO 667 FUHSING 3RD RD HWA-YA TECHNOLOGY PARK GUISHAN DIST TAOYUAN CITY 333

International Classification(s)

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  • 2014 Application Filing Year
  • H01L Class
  • 23828 Applications Filed
  • 21803 Patents Issued To-Date
  • 91.51 % Issued To-Date
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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chu, Ron Fu Taipei City, TW 15 29
Hu, Yaw-Wen Taoyuan County, TW 22 52
Lee, Tzung-Han Taipei City, TW 135 609

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Patent Citation Ranking

  • 2 Citation Count
  • H01L Class
  • 7.09 % this patent is cited more than
  • 11 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges7625916189582342423416712683684320001 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +0500100015002000250030003500400045005000550060006500

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