Effective Caching for Demand-based Flash Translation Layers in Large-Scale Flash Memory Storage Systems
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United States of America Patent
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Issued Date -
Oct 9, 2014
app pub date -
Apr 8, 2013
filing date -
Apr 8, 2013
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Abstract
This invention discloses methods for implementing a flash translation layer in a computer subsystem comprising a flash memory and a random access memory (RAM). According to one disclosed method, the flash memory comprises data blocks for storing real data and translation blocks for storing address-mapping information. The RAM includes a cache space allocation table and a translation page mapping table. The cache space allocation table may be partitioned into a first cache space and a second cache space. Upon receiving an address-translating request, the cache space allocation table is searched to identify if an address-mapping data structure that matches the request is present. If not, the translation blocks are searched for the matched address-mapping data structure, where the physical page addresses for accessing the translation blocks are provided by the translation page mapping table. The matched address-translating data structure is also used to update the cache space allocation table.
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