PROGRAMMABLE IMPEDANCE MEMORY ELEMENTS AND CORRESPONDING METHODS

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United States of America Patent

SERIAL NO

14195787

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Abstract

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A memory element programmable between different impedance states can include a first electrode; a switching layer formed in contact with the first electrode and including at least one metal oxide; and a buffer layer in contact with the switching layer. A buffer layer can include a first metal, tellurium, a third element, and a second metal distributed within the buffer layer. A second electrode can be in contact with the buffer layer.

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Patent Owner(s)

Patent OwnerAddress
ADESTO TECHNOLOGIES CORPORATION1250 BORREGAS AVENUE SUNNYVALE CA 94089

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gopalan, Chakravarthy Santa Clara, US 19 384
Gopinath, Venkatesh P Fremont, US 46 196
Jameson, John Ross Menlo Park, US 8 67
Lee, Wei Ti San Jose, US 45 1637
Ma, Yi Santa Clara, US 122 3864
Sanchez, John Palo Alto, US 68 1159
Shields, Jeffrey Allan Sunnyvale, US 10 19
Tsai, Kuei Chang Cupertino, US 10 22
Van, Buskirk Michael Saratoga, US 18 342
Wang, Janet Los Altos, US 18 326

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