Memory Patching Circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Sep 25, 2014
app pub date -
Sep 16, 2013
filing date -
Mar 25, 2013
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A patching circuit for patching a memory 2 is disclosed. An address register 1 is configured to store a first memory address. A comparison unit 4 is configured to receive a second memory address from an address bus 5, and to receive the first memory address. The comparison unit is further configured to compare the first memory address with the second memory address. A selecting unit 7 is configured to receive a value from a data register 3 associated with the address register 1, and a value from an input data bus 8, wherein the second value corresponds to the value stored in a position of the memory 2 identified by the second memory address. The selecting unit 7 is further configured to select one of the values based on the comparison performed, and to send the value to an output data bus 10.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully