Method for Forming Fine Patterns of Semiconductor Device Using Directed Self-Assembly Process
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United States of America Patent
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Issued Date -
Sep 25, 2014
app pub date -
Sep 27, 2012
filing date -
Sep 29, 2011
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Abandoned
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Abstract
Provided herein is a method for forming fine patterns of semiconductor devices capable of forming patterns with 20 nm-level line width without bulk-exposure and hardening of guide patterns. Method steps include (a) forming a photoresist layer over a wafer on which an organic anti-reflection coating layer is formed; (b) exposing and developing the photoresist layer to form guide patterns; (c) forming a neutral layer over the wafer; (d) developing the guide patterns to remove them and form neutral layer patterns having an opening part; (e) coating block copolymer of directed self assembly material on the substrate and heating the substrate over a glass transition temperature (Tg) to form directed self-assembly patterns; and (f) selectively etching a part having relatively small etching resistivity (or high etching rate) among the directed self-assembly patterns by using O2 plasma to form fine patterns.
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