MULTI-DIMENSIONAL ERROR DETECTION AND CORRECTION MEMORY AND COMPUTING ARCHITECTURE
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United States of America Patent
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Issued Date -
Sep 18, 2014
app pub date -
Mar 15, 2013
filing date -
Mar 15, 2013
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Abandoned
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Abstract
Error correction and detection may be performed across multiple dimensions of memory storage, such as across two or more complete memory devices, as well as within individual pages of memory within a single memory device. Error correction and detection performed across two or more complete memory devices may mitigate single event functional interrupts that affect a complete memory device. Error detection and correction performed within individual pages of memory may be used to mitigate single event upset induced single and multiple bit flips within a page of a memory device. A parallel or serial block code, such as a parallel or serial block Reed-Solomon code or any other type of error correcting code, may be used for error correction and detection performed across two or more complete memory devices or within individual pages of memory within a single memory device.
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