DUAL DATA RATE BRIDGE CONTROLLER WITH ONE-STEP MAJORITY LOGIC DECODABLE CODES FOR MULTIPLE BIT ERROR CORRECTIONS WITH LOW LATENCY
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United States of America Patent
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Issued Date -
Sep 18, 2014
app pub date -
Mar 17, 2014
filing date -
Mar 15, 2013
priority date (Note) -
Abandoned
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Abstract
A memory module includes a bridge controller having a first interface and a second interface. The first interface receives commands and data from a host and the second interface is coupled to one or more memory components. The bridge controller performs multiple-bit error detection and correction on data stored in the one or more memory components.
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