ADDRESS TRANSLATION IN A SYSTEM USING MEMORY STRIPING
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United States of America Patent
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Issued Date -
Sep 18, 2014
app pub date -
Mar 6, 2014
filing date -
Mar 15, 2013
priority date (Note) -
Abandoned
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Abstract
A system and associated methods are disclosed for translating virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a virtual memory address, comparing a portion of the received virtual memory address to each of a plurality of entries of a virtual memory address matching table, determining a matching row of the virtual memory address matching table for the portion of the received virtual memory address, shifting a contiguous set of bits of the received virtual memory address, wherein the shifting is performed in accordance with information from the matching row, and combining the shifted contiguous set of bits of the received virtual memory address with high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table, and with low-order bits of the received virtual memory address, to produce a physical memory address.
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