Low-power CML-less transmitter architecture
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United States of America Patent
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Aug 16, 2016
Grant Date -
Sep 18, 2014
app pub date -
Mar 15, 2013
filing date -
Mar 15, 2013
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Abstract
Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.
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