HETEROJUNCTION TRANSISTOR AND METHOD OF FABRICATING THE SAME
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Sep 11, 2014
app pub date -
Mar 6, 2014
filing date -
Mar 8, 2013
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Exemplary embodiments of the present invention disclose a heterojunction transistor having a normally off characteristic using a gate recess structure and a method of fabricating the same. The heterojunction transistor may include a substrate, a channel layer disposed on the substrate and made of a first nitride-based semiconductor having a first energy bandgap, a first barrier layer disposed on the channel layer and made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, a gate electrode disposed in a gate control region of the first barrier layer, and a second barrier layer disposed in gate non-control regions of the first barrier layer and separated from the first barrier layer.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully