METHOD FOR FABRICATING NONVOLATILE MEMORY STRUCTURE
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United States of America Patent
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Issued Date -
Aug 28, 2014
app pub date -
May 14, 2014
filing date -
Dec 27, 2012
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Abandoned
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Abstract
A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions.
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