METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

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United States of America Patent

APP PUB NO 20140235016A1
SERIAL NO

14155243

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Abstract

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Provided is a method of fabricating a semiconductor package, including preparing a die including a first metal layer and a second metal layer which are sequentially stacked on a silicon substrate, preparing a package substrate including a lead frame, and forming an adhesive layer between the lead frame and the first metal layer and attaching the die to the package substrate, wherein the forming of the adhesive layer is performed by eutectic bonding between the silicon substrate and the second metal layer. According to the semiconductor package according to an embodiment of the present invention, an adhesive layer can be easily formed by eutectic bonding without a process of forming a preform.

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Patent Owner(s)

Patent OwnerAddress
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEDAEJEON
SIGETRONICS INC402 JEONBUK UNIV 664-14 DEOKJIN-DONG 1-GA DEOKJIN-GU JEOLLABUK-DO JEONJU-SI 561-807

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHO, Deok-Ho Seoul, KR 17 239
LEE, Jin Ho Daejeon, KR 905 7012
PARK, Jong-Moon Daejeon, KR 9 100
SHIM, Kyu-Hwan Jeonju-si, KR 6 38

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