METHOD OF FABRICATING SEMICONDUCTOR DEVICE

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United States of America Patent

SERIAL NO

14259702

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Abstract

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In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATIONTOKYO 135-0061

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
IMAI, Yasuo Takasaki-shi, JP 48 432
KOBAYASHI, Masayoshi Takasaki-shi, JP 123 1688
KUBO, Sakae Takasaki-shi, JP 18 242
KUDO, Satoshi Maebashi-shi, JP 77 782
NAKAZAWA, Yoshito Takasaki-shi, JP 108 1477
NUMAZAWA, Sumito Takasaki-shi, JP 16 221
OHNISHI, Akihiro Isesaki-shi, JP 20 285
OISHI, Kentaro Takasaki-shi, JP 36 330
SHIGEMATSU, Takashi Takasaki-shi, JP 93 1340
UESAWA, Kozo Sawa-gun, JP 16 221

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