DYNAMIC SCALING PROCESSOR DEVICE AND PROCESSING METHOD THEREOF
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United States of America Patent
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Issued Date -
Jul 31, 2014
app pub date -
Aug 6, 2013
filing date -
Jan 25, 2013
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Abandoned
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Abstract
A dynamic scaling processor device and processing method thereof, having a timing decoder, a multi-cycle controller, a correction flip-flop. The timing decoder is provided with a plurality of cycles therein, to receive a plurality of instructions, to select corresponding cycles as its predetermined cycles based on type of each instruction, and output the predetermined cycles and its corresponding instructions to the multi-cycle controller. The multi-cycle controller computes results of the instructions based on the predetermined cycles or a single cycle, and outputs them to the correction flip-flop. The error detection flip-flop utilizes a first clock signal and a stalled second clock signal, to sample a same result, and correct the results when outcomes of samplings are different.
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