SYSTEM AND METHOD OF WEAR LEVELING FOR A NON-VOLATILE MEMORY
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United States of America Patent
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Issued Date -
Jul 24, 2014
app pub date -
Jan 21, 2013
filing date -
Jan 21, 2013
priority date (Note) -
Abandoned
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Abstract
In an architecture of wear leveling for a non-volatile memory composed of plural storage units, a translation layer is configured to translate a logical address provided by a host to a physical address of the non-volatile memory. A cold-block table is configured to assign a cold block or blocks in at least one storage unit, the cold block in a given storage unit having an erase count being less than erase counts of non-cold blocks in the given storage unit. The logical addresses and the associated physical addresses of the cold blocks are recorded in the cold-block table, thereby building a cold-block pool composed of the cold blocks.
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