FLIP-CHIP WAFER LEVEL PACKAGE AND METHODS THEREOF
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United States of America Patent
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app pub date -
Mar 26, 2014
filing date -
Dec 31, 2012
priority date (Note) -
Abandoned
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Abstract
An electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package.
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