Techniques For Forming 3D Structures

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United States of America Patent

APP PUB NO 20140193963A1
SERIAL NO

14208303

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A technique for forming 3D semiconductor structure is disclosed. In one embodiment, a substrate having at least two vertically extending fins is provided. An insulating material is deposited in the trench between the fins. After planarization, an ion implant process is performed to change the properties of the insulating material, specifically, the implanted region has a higher etch rate than the remainder of the insulating material. This higher etch rate region is then removed. This process of implanting and removing can be repeated until the insulating material reaches the desired height. In some embodiments, the substrate may be subjected to an anneal process prior to the removal of the higher etch rate region. The Gaussian implant depth profile may change into a box-like implant depth profile during the anneal process via thermal diffusion.

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Patent Owner(s)

Patent OwnerAddress
VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES INC35 DORY ROAD GLOUCESTER MA 01930

International Classification(s)

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  • 2014 Application Filing Year
  • H01L Class
  • 23828 Applications Filed
  • 21803 Patents Issued To-Date
  • 91.51 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2014201520162017201820192020202120222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Godet, Ludovic Sunnyvale, US 327 3246
Han, Keping Lexington, US 3 17

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Patent Citation Ranking

  • 6 Citation Count
  • H01L Class
  • 7.09 % this patent is cited more than
  • 11 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges7625916189582342423416712683684320001 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +0500100015002000250030003500400045005000550060006500

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