Techniques For Forming 3D Structures
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jul 10, 2014
app pub date -
Mar 13, 2014
filing date -
May 16, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A technique for forming 3D semiconductor structure is disclosed. In one embodiment, a substrate having at least two vertically extending fins is provided. An insulating material is deposited in the trench between the fins. After planarization, an ion implant process is performed to change the properties of the insulating material, specifically, the implanted region has a higher etch rate than the remainder of the insulating material. This higher etch rate region is then removed. This process of implanting and removing can be repeated until the insulating material reaches the desired height. In some embodiments, the substrate may be subjected to an anneal process prior to the removal of the higher etch rate region. The Gaussian implant depth profile may change into a box-like implant depth profile during the anneal process via thermal diffusion.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES INC | 35 DORY ROAD GLOUCESTER MA 01930 |
International Classification(s)

- 2014 Application Filing Year
- H01L Class
- 23828 Applications Filed
- 21803 Patents Issued To-Date
- 91.51 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Godet, Ludovic | Sunnyvale, US | 327 | 3246 |
# of filed Patents : 327 Total Citations : 3246 | |||
Han, Keping | Lexington, US | 3 | 17 |
# of filed Patents : 3 Total Citations : 17 |
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Patent Citation Ranking
- 6 Citation Count
- H01L Class
- 7.09 % this patent is cited more than
- 11 Age
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11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jan 10, 2026 |
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