Importance

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Abstract

A semiconductor memory device has a memory cell array with memory cells, each including first and second conduction type transistors, column-side peripheral circuits disposed with the same row-direction interval as the memory cells, a first conduction type well region formed within the memory cell array, a second conduction type well region formed within the first conduction type well region and is disposed separately in the row direction, a second conduction type well contact region disposed extending in the row direction among the memory cells, a first conduction type well contact region disposed extending in the column direction among the memory cells, a column-side peripheral contact region, a first conduction type back gate voltage line connecting to the first conduction type well region; and a second conduction type back gate voltage line connecting to the second conduction type well.

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First Claim