Logic circuits with and-not gate for fast fuzzy decoders
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United States of America Patent
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Jun 20, 2017
Issued Date -
N/A
app pub date -
Feb 5, 2014
filing date -
Dec 14, 2010
priority date (Note) -
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Abstract
A logic decoder circuit capable of performing Boolean or fuzzy logic has one or more logic components configured to perform a logic function of an AND-NOT gate, each AND-NOT gate comprising a circuit that performs a conjunction of an excitatory input X and an inhibitory input Y to obtain an output X-AND-NOT-Y substantially linearly for given ranges for X and Y. Certain preferred designs are provided for an X-AND-NOT-Y logic gate and a family of fast fuzzy decoders composed of such gates.
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International Classification(s)
- 2014 Application Filing Year
- G06N Class
- 1974 Applications Filed
- 1226 Patents Issued To-Date
- 62.11 % Issued To-Date
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- 0 Citation Count
- G06N Class
- 0 % this patent is cited more than
- 8 Age
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