METHOD OF FORMING A TOP GATE TRANSISTOR
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United States of America Patent
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Issued Date -
Jun 5, 2014
app pub date -
Jul 13, 2012
filing date -
Jul 21, 2011
priority date (Note) -
Abandoned
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Abstract
A method of forming a top-gate transistor over a substrate comprises: forming a source and a drain electrode; forming an organic stack over the source and drain electrodes comprising an organic semiconductor layer and an organic dielectric layer over the organic semiconductor layer; forming a gate bi-layer electrode comprising a first gate layer of a first material and a second gate layer of a different second material; selectively depositing regions of a mask material over the gate bi-layer electrode; performing a first plasma etch step to remove portions of the first gate layer using the mask material as a mask; and performing a second plasma etch step to remove portions of the second gate layer and organic stack using the first gate layer as a mask, thereby patterning the gate bi-layer electrode and the organic stack.
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