METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE
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United States of America Patent
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app pub date -
Dec 31, 2013
filing date -
Oct 23, 2012
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Abandoned
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Abstract
A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.
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