Method for Integrating MnOz Based Resistive Memory with Copper Interconnection Back-End Process
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United States of America Patent
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Issued Date -
Apr 24, 2014
app pub date -
Jul 6, 2011
filing date -
Jul 6, 2011
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Abstract
The present invention pertains to the technical field of semiconductor memory. More particularly, the invention relates to a method for integrating MnOz based resistive memory with copper interconnection back-end process. In the method for integrating with the process, a MnSi compound layer is firstly formed by silicifying Mn metal in the cap layer on Cu wire, a MnSixOy storage medium layer is formed by oxidizing the MnSi compound layer, and a MnSiO compound layer serves as a barrier layer for Cu wire in the copper interconnection back-end. The method has the advantage of be easily compatible with a copper interconnection back-end process at or below 45 nm process node. The MnOz based resistive memory is low in fabrication cost, high in reliability and low in power consumption.
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