Semiconductor Unit with Submount for Semiconductor Device
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United States of America Patent
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Issued Date -
Apr 24, 2014
app pub date -
Dec 30, 2013
filing date -
Jun 17, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A semiconductor unit includes a submount and a chip coupled to the submount. The submount is configured with a base and a plurality of layers between the base and the chip. One of the layers, a heat-spreading electro-conducting sliver (“Ag”) layer, is deposited atop the base. The thickness of the Ag layer is selected so that a cumulative coefficient of thermal expansion of the submount substantially matches that one of the chip. Coupled to the active zone of the chip is a stress-dumping layer made from elastic malleable materials.
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