INTEGRATION VERIFICATION SYSTEM

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20140100837A1
SERIAL NO

13646789

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A verification system for an integrated device includes a plurality of detailed subsystem virtual prototypes, a plurality of fast subsystem virtual prototypes, and a test controller. The plurality of detailed system virtual prototypes include simulation information for core functionality of subsystems of the device. The plurality of fast system level prototypes include simulation information to facilitate overall functionality of the combined subsystems of the device.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brock, Juergen Ottobrunn, DE 1 6
Gowde, Shrinivas Rao K Bangalore, IN 1 6
Heinen, Stefan Dueren, DE 20 160
Hoelscher, Jonas Duesseldorf, DE 1 6
Magerl, Goran Duesseldorf, DE 1 6
Paragond, Rajshekhar N Bangalore, IN 1 6
Radhakrishnan, Sindhura Bangalore, IN 1 6
Ramachandrarao, Ragu T Bangalore, IN 1 6

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