High breakdown voltage III-N depletion mode MOS capacitors
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United States of America Patent
Stats
-
Jun 23, 2015
Grant Date -
Apr 3, 2014
app pub date -
Sep 28, 2012
filing date -
Sep 28, 2012
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.
First Claim
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International Classification(s)
- 2012 Application Filing Year
- H01L Class
- 20465 Applications Filed
- 18077 Patents Issued To-Date
- 88.34 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 3 Citation Count
- H01L Class
- 10.46 % this patent is cited more than
- 10 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Dec 23, 2026 |
