SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THEREOF

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United States of America Patent

APP PUB NO 20140091397A1
SERIAL NO

14041984

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Abstract

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It is therefore an object of the present invention to provide a method in which, in a semiconductor integrated circuit device, a plurality of transistors having wide-rangingly different Ioff levels are embedded together in a semiconductor device including transistors each using a non-doped channel. By controlling an effective channel length, a leakage current is controlled without changing an impurity concentration distribution in a transistor including a non-doped channel layer and a screen layer provided immediately under the non-doped channel layer.

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Patent Owner(s)

Patent OwnerAddress
FUJITSU SEMICONDUCTOR LIMITEDKOHOKU-KU YOKOHAMA-SHI KANAGAWA 222-0033

International Classification(s)

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  • 2013 Application Filing Year
  • H01L Class
  • 22267 Applications Filed
  • 20713 Patents Issued To-Date
  • 93.03 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2013201420152016201720182019202020212022202320240255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ema, Taiji Inabe, JP 186 2365
Fujita, Kazushi Kuwana, JP 27 94
Hori, Mitsuaki Kuwana, JP 28 260
Torii, Yasunobu Kuwana, JP 13 20

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Patent Citation Ranking

  • 4 Citation Count
  • H01L Class
  • 7.09 % this patent is cited more than
  • 11 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges7625916189582342423416712683684320001 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +0500100015002000250030003500400045005000550060006500

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