CHIP PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING STRUCTURE HAVING SAME
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United States of America Patent
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Issued Date -
Mar 27, 2014
app pub date -
Sep 17, 2013
filing date -
Sep 25, 2012
priority date (Note) -
Abandoned
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Abstract
A chip packaging substrate includes a dielectric layer, a first inner wiring layer embedded in the dielectric layer, an outer wiring layer, and many conductive connection points. The outer wiring layer is formed at one side of the dielectric layer, and is electrically connected to the first inner wiring layer through many first conductive vias in the dielectric layer. The conductive connection points are formed at the other side of the dielectric layer, and are electrically connected to the first inner wiring layer through many second conductive vias in the dielectric layer.
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