SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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United States of America Patent
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Issued Date -
Mar 27, 2014
app pub date -
Sep 23, 2013
filing date -
Sep 27, 2012
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Abandoned
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Abstract
Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.
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