Extended Source-Drain MOS Transistors And Method Of Formation

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United States of America Patent

APP PUB NO 20140084367A1
SERIAL NO

13974936

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A transistor and method of making same include a substrate, a conductive gate over the substrate and a channel region in the substrate under the conductive gate. First and second insulating spacers are laterally adjacent to first and second sides of the conductive gate. A source region in the substrate is adjacent to but laterally spaced from the first side of the conductive gate and the first spacer, and a drain region in the substrate is adjacent to but laterally spaced apart from the second side of the conductive gate and the second spacer. First and second LD regions are in the substrate and laterally extend between the channel region and the source or drain regions respectively, each with a portion thereof not disposed under the first and second spacers nor under the conductive gate, and each with a dopant concentration less than that of the source or drain regions.

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Patent Owner(s)

Patent OwnerAddress
SILICON STORAGE TECHNOLOGY INC450 HOLGER WAY SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Yueh-Hsin Pleasanton, US 7 17
Su, Chien-Sheng Saratoga, US 46 662
Tadayoni, Mandana Cupertino, US 14 97

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