ARBITRATING BETWEEN DATA PATHS IN A BUFFERLESS FREE FLOWING INTERCONNECT
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United States of America Patent
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Issued Date -
Mar 20, 2014
app pub date -
Sep 19, 2012
filing date -
Sep 19, 2012
priority date (Note) -
Abandoned
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Abstract
An interconnect comprising paths configured to transmit data packets between nodes on a network. The nodes comprise ports for inputting and outputting the data packets to the interconnect. At least two of the paths each have at least a portion configured such that a data packet addressed for output at one of the nodes on one of the paths and not being accepted at the node will continue along the path and on travelling further will return to the node. The at least two paths are balanced paths such that a data packet not accepted at the one of the nodes will return to the node a same predetermined number of clock cycles later whichever of the balanced paths the data packet is traveling along. The one of the nodes comprises an arbiter that is configured to prioritise one of the balanced data paths for output, the arbiter being configured to ensure that a priority changes after the predetermined number of clock cycles, such that a data packet on any of the balanced paths not being accepted for output at the node on a first attempt is guaranteed to have priority on a subsequent return to the node.
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