Heterostructure Transistor with Multiple Gate Dielectric Layers
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United States of America Patent
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Mar 20, 2014
app pub date -
Sep 14, 2012
filing date -
Sep 14, 2012
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Abstract
A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A first gate dielectric layer is disposed on the second active layer. A second gate dielectric layer is disposed on the first gate dielectric layer. A passivation layer is disposed over the second gate dielectric layer. A gate extends through the passivation layer to the second gate dielectric layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.
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