HYBRID DECODING OF BCH CODES FOR NONVOLATILE MEMORIES
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United States of America Patent
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Issued Date -
Mar 6, 2014
app pub date -
Oct 13, 2011
filing date -
Oct 13, 2011
priority date (Note) -
Abandoned
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Abstract
An apparatus and a method for correcting data errors in a data block. The data block contains original data which are supplemented by such a security syndrome that the data block effects a correction of at most t data errors, wherein a parallel-operating quick corrector is used. The quick corrector is only designed for a correction of a subset t1 of the set of the at most t data errors, and the quick corrector includes a test encoder, which sets a first test state flag P1 which, in the event of a complete correction of a processed data block, outputs this data block and secondly activates a series-operating post-corrector for at most t data errors. The output signal of the post-corrector is output as an alternative.
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