METHOD FOR MAKING A DOUBLE-SIDED FANOUT SEMICONDUCTOR PACKAGE WITH EMBEDDED SURFACE MOUNT DEVICES, AND PRODUCT MADE
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United States of America Patent
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Issued Date -
Feb 27, 2014
app pub date -
Aug 24, 2012
filing date -
Aug 24, 2012
priority date (Note) -
Abandoned
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Abstract
A manufacturing process includes forming a reconstituted wafer, including embedding semiconductor dice in a molding compound layer and forming through-wafer vias in the layer. A fan-out redistribution layer is formed on a front side of the wafer, with electrical traces interconnecting the dice, through-wafer vias, and contact pads positioned on the redistribution layer. Solder balls are positioned on the contact pads and a molding compound layer is formed on the redistribution layer, reinforcing the solder balls. A second fan-out redistribution layer is formed on a back side of the wafer, with electrical traces interconnecting back ends of the through-wafer vias and contact pads positioned on a back face of the second redistribution layer. Flip-chips and/or surface-mounted devices are coupled to the contact pads of the second redistribution layer and encapsulated in an underfill layer formed on the back face of the second redistribution layer.
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