SATURATION CURRENT LIMITING CIRCUIT TOPOLOGY FOR POWER TRANSISTORS
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United States of America Patent
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Issued Date -
Feb 27, 2014
app pub date -
Jun 26, 2013
filing date -
Aug 24, 2012
priority date (Note) -
Abandoned
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Abstract
A circuit topology for limiting saturation current in power transistors is disclosed. The circuit topology includes a normally-on transistor and a normally-off transistor coupled in series. A limiter circuit is coupled between a gate of the normally-on transistor and a source of the normally-off transistor for limiting the steady-state maximum gate-to-source voltage VGS of the normally-on transistor, which in turn limits the saturation current that flows through the normally-on transistor and the normally-off transistor.
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